Current trends in integrated circuit designs call for creating an entire manufactured circuit system on a single chip. Such a system is termed system-on-chip or SOC. This differs from simple circuit integration in that many different types of circuits can be included on a single chip. For example, an SOC could include a computer processor, various signal processors, a large amount of memory, various clocks, power down circuits, and necessary system controllers all integrated on a single piece of silicon or integrated into a single package. This level of integration was not previously possible with prior integration techniques, and is very advantageous because useful devices can be created in very small sizes.
FIG. 1 is a block diagram showing an SOC 10a The SOC 10a is formed of a number of different integrated circuit portions (IPs) or blocks 12, 14, . . . , 20. Each IP block 12–20 is connected to a system clock 30. The system clock 30 distributes a system clock signal to each of the IP blocks 12–20.
Important examples of devices that can include SOCs are cellular phones, palmtops, notebooks, computer components, movable equipment, communication apparatuses, biomedical apparatuses, digital cameras, MP3 players, etc. Such applications generally require a battery or some sort of power supply, which typically presents cost, duration, weight and dimension issues. To increase the longevity of the power supplies for these devices, and especially for portable devices which require a portable power source, power consumption of the SOCs must be reduced from their current levels.
Dynamic power consumption of the different circuits blocks 12–20 integrated on a single SOC 10a is given by the formula P=f*C*v*2, where P is power, f is operating frequency of a circuit block, C is capacitance of all of the gates of the circuit block, and v is the power supply voltage. Therefore, in addition to reducing the power supply voltage and the overall capacitance, power of the SOC 10a may be conserved by reducing the operating frequency of the different circuit blocks 12–20. One way to implement this is to temporarily switch off the system clock for some of the IP blocks 12–20 of the SOC 10a that are not necessary for immediate functions. Because not all of the IP blocks 12–20 necessarily operate at the same time in the SOC 10a, some of them are unused and are eligible to be shutdown.
FIG. 2 shows an SOC 10b that is similar to the SOC 10a of FIG. 1, but additionally includes a power control manager 40. The power control manager 40 controls a bank of switches 42 that are coupled between the system clock 30 and the various IP blocks 12–20. When the power control manager 40 determines that particular IP blocks should be shutdown, such as circuit blocks 14 and 16, for example, a signal is generated and fed to the bank of switches 42. The bank of switches 42 then controls the particular switch coupled to the selected IP blocks, in this example IP blocks 14 and 16, and disconnects them from the system clock 30. When the selected IP blocks 14, 16 do not receive the system clock 30, they stop functioning and, based upon the above equation, do not draw any power because the operating frequency of the circuit is brought to zero.
Although the idea of separating the system clock from the various IP blocks is compelling, most SOCs cannot be controlled in such a manner. The implementation of such a system as shown in FIG. 2 causes problems. As described above, many different types of IP blocks are contained within a particular SOC, and each of these IP blocks have unique requirements for when they can be safely shutdown.
It can therefore be difficult to establish an exact time when it is possible to switch off the clock to an IP block without causing errors. In some cases, if the clock to the IP block is stopped abruptly, there is a risk of preventing a critical operation of the block from being carried out. For example, an IP block could be performing a necessary communication protocol and the shutdown of the block could cause the SOC to disregard the protocol. Examples of protocols that could easily be disregarded include memory-DMA, and master-slave blocks among others. Additionally, removing a system clock from a counter or a timing signal generator could be fatal to that particular IP block.
Some of these problems are illustrated in FIG. 3, which shows an SOC 10c that has prevented the system clock 30 from reaching the IP blocks 14, 16 and 18, while continuing to supply the IP blocks 12 and 20. In each of the cases of the non-supplied blocks 14, 16, 18, there are potential problems. For instance, the IP block 14 may be in the middle of a memory-DMA protocol operation with a memory unit 24, and its abrupt halt may violate that protocol. Similarly, the IP block 16 may be communicating with a slave peripheral 26, and an abrupt halt may cause a malfunction or protocol violation. Additionally, the IP block 18 may include counters which rely on the system clock 30 for accuracy. Separating the system clock 30 from the IP block 18 could seriously degrade such accuracy.